European Sovereignty
Work package 2 carries out the task of Co-design of Plasma Simulation Codes with the European Processor and Accelerator. The objective of this work package led by FORTH, is:
“to ensure the co-design of Plasma-PEPSC codes with the EPI processor, the SIPEARL Rhea, and the EPI RISC-V accelerator. ”
The following goals express the vision for Work Package 2 more specifically:
● Study the codes of the Plasma community with the aim of identifying potential for leveraging architectural features of EPI systems (e.g., Arm-based general-purpose CPUs with HBM and RISC-V CPUs with large vector processing units).
● Profile and benchmark Plasma codes on the current Arm-based HPC system.
● Port and execute Plasma codes on current RISC-V commercial systems.
● Analyze Plasma codes (or mini-apps when complexity does not allow working on full-size codes) to identify potential for vectorization with the goal of leveraging both Arm SVE extension and RISC-V vector extension.
● Collect feedback from the study to either improve the EPI system software or enhance the Plasma codes, enabling vectorization without compromising portability.
The Co-design Tasks
This work package is split into three tasks, as follows:
● Task 2.1: Experiences and application co-design with the European Processor. This task is led by SIPEARL with contributions from MPG, UoH, HZDR, UL, IPP CAS, KTH.
Plasma-PEPSC plasma simulation developers (BIT, GENE, PIConGPU, and Vlasiator) and SIPEARL work very closely to
1) analyse the current applications, how they can efficiently use SVE256, using the profiling tools provided by SIPEARL.
2) Profile the applications and reference datasets to understand which parts can efficiently take advantage of the HBM, which parts do not require it.
3) Profile the applications and reference datasets to understand which parts can efficiently take advantage of the CPU in regards to the GPUs and other accelerators. Data movement between the processor and accelerator memory spaces will be carefully analyzed to understand how to take advantage of CXL2 new features.
● Task 2.2: Experiences and application co-design with the European Accelerator. This task is led by BSC with contributions from FORTH, MPG, UoH, HZDR, UL, IPP CAS, KTH.
The goal of this task is to provide access and support to the RISC-V based Software Development Vehicle (SDV) made available by the European Processor Initiative (EPI) and EUPilot projects. SDV are software and hardware system prototypes that allow experimentation with architectures leveraging lean cores coupled with long vector processing units.
● Task 2.3: Plasma Simulations and Future Emerging Technologies. This task is led by KTH with contributions from MPG.
The goal of this task is to investigate and explore the role of new emerging technologies, such as quantum computing, on the development of algorithms and software for plasma simulations in the post-exascale era. This task reviews the state-of-the-art of plasma algorithms, e.g. Vlasov solvers, for Noisy Intermediate Scale Quantum and other promising disruptive computing approaches. This task also investigates the integration of these approaches into traditional HPC codes as hybrid models and HPC infrastructure.